View IDT72251L20J_25575.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CMOS SyncFIFOTM 8192 X 9
Integrated Device Technology, Inc.
ADVANCED INFORMATION IDT72251
FEATURES:
* * * * * * * * * * * * 8192 x 9-bit organization Pin/function compatible with IDT72421/722x1 family 15 ns read/write cycle time Read and write clocks can be independent Dual-Ported zero fall-through time architecture Empty and Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags can be set to any depth Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output enable puts output data bus in high-impedance state Advanced submicron CMOS technology Available in 32-pin plastic leaded chip carrier (PLCC) Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72251 SyncFIFOTM is a very high-speed, lowpower First-In, First-Out (FIFO) memory with clocked read and write controls. The IDT72251 has a 8192 x 9-bit memory array. This FIFO is applicable for a wide variety of data buffering needs such as graphics, local area networks and
interprocessor communication. This FIFO has a 9-bit input and output port. The input port is controlled by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two read enable pins (REN1, REN2). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output. The Synchronous FIFO has two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin (LD). The IDT72251 is fabricated using IDT's high-speed submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK WEN2 INPUT REGISTER OFFSET REGISTER D0 - D8
WRITE CONTROL LOGIC
FLAG LOGIC
WRITE POINTER
RAM ARRAY 8192 x 9
READ POINTER
READ CONTROL LOGIC
OUTPUT REGISTER RESET LOGIC
RCLK
Q0 - Q8
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
3545 drw 01
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-3545/-
5.14
1
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
D2 D3 D4 D5 D6 D7 D8
INDEX
4 D1 D0 PAF PAE GND REN1 RCLK REN2 OE 5 6 7 8 9 10 11 12 13
3
2 1
32 31 30 29 28 27 26
RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5
J32-1
25 24 23 22
21 14 15 16 17 18 19 20
Q3 Q0 Q1 Q2 Q4 EF FF
PLCC TOP VIEW
2655 drw 02b
PIN DESCRIPTIONS
RS
Symbol D0-D8
Name Data Inputs Reset
WCLK
Write Clock Write Enable 1
WEN1
WEN2/LD
Write Enable 2/ Load
Q0-Q8 RCLK
Data Outputs Read Clock Read Enable 1 Read Enable 2 Output Enable Empty Flag
REN1 REN2 OE EF PAE PAF FF
VCC GND
Programmable Almost-Empty Flag Programmable O Almost-Full Flag Full Flag O Power Ground
I/O Description I Data inputs for a 9-bit bus. I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/ LD is HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. O Data outputs for a 9-bit bus. I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default offset at reset is Empty+7. PAE is synchronized to RCLK. When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The default offset at reset is Full-7. PAF is synchronized to WCLK. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. One +5 volt power supply pin. One 0 volt ground pin.
2655 tbl 01
5.14
2
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Unit V
RECOMMENDED OPERATING CONDITIONS
Symbol VCCC GND VIH VIL Parameter Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Commercial Min. 4.5 0 2.0 -- Typ. 5.0 0 -- -- Max. 5.5 0 -- 0.8 Unit V V V V
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
C C C mA
2655 tbl 02
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN(2) COUT
(1,2)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
NOTES: 1. With output deselected (OE = HIGH). 2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C)
IDT72251 Commercial tCLK = 15, 20, 25, 35 Typ. Max. -- -- -- -- -- 1 10 -- 0.4 80
Symbol ILI(1) ILO(2) VOH VOL ICC1(4)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage, IOH = -2mA Output Logic "0" Voltage, IOL = 8mA Active Power Supply Current
Min. -1 -10 2.4 -- --
Unit A A V V mA
NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3 & 4. Measurements are made with outputs unloaded. Tested at fCLK = 20MHz. (3) Typical ICC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA (4) Typical ICC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA fCLK = 1/tCLK. CL = external capacitive load (30pF typical)
5.14
3
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C
Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset to Flag Time and Output Time Output Enable to Output in Low-Z(2) Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Write Clock to Programmable Almost-Full Flag Read Clock to Programmable Almost-Empty Flag 72251L15 Min. Max. -- 2 15 6 6 4 1 4 1 15 15 15 -- 0 3 3 -- -- -- -- 6 28 66.7 10 -- -- -- -- -- -- -- -- -- -- 15 -- 8 8 10 10 10 10 -- -- Commercial 72251L20 72251L25 Min. Max. Min. Max. -- 2 20 8 8 5 1 5 1 20 20 20 -- 0 3 3 -- -- -- -- 8 35 50 12 -- -- -- -- -- -- -- -- -- -- 20 -- 10 10 12 12 12 12 -- -- -- 3 25 10 10 6 1 6 1 25 25 25 -- 0 3 3 -- -- -- -- 10 40 40 15 -- -- -- -- -- -- -- -- -- -- 25 -- 13 13 15 15 15 15 -- -- 72251L35 Min. Max. -- 3 35 14 14 8 2 8 2 35 35 35 -- 0 3 3 -- -- -- -- 12 42 28.6 20 -- -- -- -- -- -- -- -- -- -- 35 -- 15 15 20 20 20 20 -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSKEW1 Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag tSKEW2 Skew Time Between Read Clock and Write Clock for Programmable Almost-Empty Flag and Programmable Almost-Full Flag
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
5V
1.1K D.U.T.
AC TEST CONDITIONS
In Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
2655 tbl 09
680
30pF*
2655 drw 03
or equivalent circuit Figure 1. Output Load *Includes jig and scope capacitances.
5.14
4
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS: Data In (D0 - D8) -- Data inputs for 9-bit wide data. CONTROLS: Reset (RS -- Reset is accomplished whenever the Reset RS) (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FF) and Programmable Almost-Full Flag (PAF) will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. Write Clock (WCLK) -- A write cycle is initiated on the LOW-to-HIGH transition of the write clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH transition of the write clock (WCLK). The Full Flag (FF) and Programmable Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coincident. Write Enable 1 (WEN1 -- If the FIFO is configured for WEN1) programmable flags, Write Enable 1 (WEN1) is the only enable control pin. In this configuration, when Write Enable 1 (WEN1) is low, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. If the FIFO is configured to have two write enables, which allows for depth expansion, there are two enable control pins. See Write Enable 2 paragraph below for operation in this configuration. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1) is ignored when the FIFO is full. Read Clock (RCLK) -- Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE) are synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). The write and read clocks can be asynchronous or coincident.
Read Enables (REN1 REN2 -- When both Read Enables REN1, REN2) (REN1, REN2) are LOW, data is read from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK). When either Read Enable (REN1, REN2) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. The Read Enables (REN1, REN2) are ignored when the FIFO is empty. Output Enable (OE -- When Output Enable (OE) is OE) enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-impedance state. Write Enable 2/Load (WEN2/LD) -- This is a dual-purpose L pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows depth expansion. If Write Enable 2/Load (WEN2/LD) is set high at Reset (RS = LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/ LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. In this configuration, when Write Enable (WEN1) is HIGH and/or Write Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full. The FIFO is configured to have programmable flags when the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS=low). The IDT7225 device contain four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values. If the FIFO is configured to have programmable flags when the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/ LD) are set low, data on the inputs D is written into the Empty (Least Significant Bit) offset register on the first LOW-to-HIGH transition of the write clock (WCLK). Data is written into the Empty (Most Significant Bit) offset register on the second LOW-to-HIGH transition of the write clock (WCLK), into the Full (Least Significant Bit) offset register on the third transition, and into the Full (Most Significant Bit) offset register on the fourth transition. The fifth transition of the write clock (WCLK) again writes to the Empty (Least Significant Bit) offset register.
5.14
5
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the Write Enable 2/Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write Enable 1 (WEN1) is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the Write Enable 2/Load (WEN2/LD) pin is set low and both Read Enables (REN1, REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the read clock (RCLK). A read and write should not be performed simultaneously to the offset registers.
LD 0
WEN1 0
WCLK(1)
Selection Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Into FIFO No Operation
0 1 1
1 0 1
NOTE: 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register
OUTPUTS: Full Flag (FF -- The Full Flag (FF) will go LOW, inhibiting FF) further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 8192 writes for the IDT72251. The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK). Empty Flag (EF -- The Empty Flag (EF) will go LOW, EF) inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Programmable Almost-Full Flag (PAF -- The PAF) Programmable Almost-Full Flag (PAF) will go LOW when the FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the Programmable Almost-Full Flag (PAF) will go LOW after 8192 writes for the IDT72251. The offset "m" is defined in the Full offset registers. If there is no Full offset specified, the Programmable Almost-Full Flag (PAF) will go LOW at Full-7 words. The Programmable Almost-Full Flag (PAF) is synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). Programmable Almost-Empty Flag (PAE -- The PAE) Programmable Almost-Empty Flag (PAE) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the Empty offset registers. If no reads are performed after Reset the Programmable AlmostEmpty Flag (PAE) will go HIGH after "n+1" for the IDT72251. If there is no Empty offset specified, the Programmable Almost-Empty Flag (PAE) will go LOW at Empty+7 words. The Programmable Almost-Empty Flag (PAE) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Data Outputs (Q0 - Q8) -- Data outputs for a 9-bit wide data.
72251 -- 8192 x 9-BIT 8 7 Empty Offset (LSB) Default Value 007H 8 4 (MSB) 00000 8 7 Full Offset (LSB) Default Value 007H 8 4 (MSB) 00000
Figure 3. Offset Register Location and Default Values
0
0
0
0
TABLE 1: STATUS FLAGS
NUMBER OF WORDS IN FIFO
FF
0 1 to n(1) (n+1) to (8192-(m+1) (8192-m)(2) to 8191 8192 H H H H L
PAF
H H H L L
PAE
L L H H H
EF
L H H H H
NOTES: 1. n = Empty Offset (n = 7 default value) 2. m = Full Offset (m = 7 default value)
5.14
6
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
tRS
RS
tRSS tRSR
REN1, REN2
tRSS tRSR
WEN1
tRSS WEN2/LD
(1)
tRSR
tRSF
EF, PAE
tRSF
FF, PAF
tRSF Q0 - Q8
OE = 1 OE = 0
(2)
2655 drw 06
NOTES: 1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. 2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
5.14
7
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH WCLK tDH tDS D0 - D8 DATA IN VALID tENS tENH NO OPERATION tCLKL
WEN1
WEN2/ (If Applicable) tWFF tWFF
NO OPERATION
FF
tSKEW1(1) RCLK
REN1, REN2
2655 drw 07
NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 5. Write Cycle Timing
5.14
8
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH RCLK tENH tCLKL
REN1, REN2
tENS NO OPERATION tREF tREF
EF
tA Q0 - Q8 tOLZ tOHZ tOE VALID DATA
OE
tSKEW1 (1) WCLK
WEN1
WEN2
2655 drw 08
NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle Timing
Figure 6. Read Cycle Timing
5.14
9
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
WCLK tDS
D0 - D8 D0 (First Valid tENS
D1
D2
D3
WEN1
WEN2 (If Applicable) tFRL (1) tSKEW1 RCLK tREF
EF
REN1, REN2
tA Q0 - Q8 tOLZ tOE D0 tA D1
OE
2655 drw 09
NOTE: 1. When tSKEW1 minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EF = LOW). Figure 7. First Data Word Latency Timing
5.14
10
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
NO WRITE WCLK tSKEW1 D0 - D8 tWFF tWFF tDS
NO WRITE
tSKEW1
tDS DATA WRITE
tWFF
FF
WEN1
WEN2 (If Applicable)
RCLK tENS tENH tENS tENH
REN1, REN2
LOW
tA
OE
tA
Q0 - Q8
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2655 drw 10
Figure 8. Full Flag Timing
5.14
11
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
WCLK tDS tDS
D0 - D8 tENS
DATA WRITE 1 tENH tENS
DATA WRITE 2 tENH
WEN1
tENS WEN2 (If Applicable) tSKEW1 RCLK tREF tREF tREF tENH tENS tENH
tFRL(1) tSKEW1
tFFL
(1)
EF REN1, REN2
OE
LOW tA
Q0 - Q8
DATA IN OUTPUT REGISTER
DATA READ
2655 drw 11
NOTE: 1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
5.14
12
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLKH WCLK
tCLKL
(4)
tENS
tENH
WEN1
tENS WEN2 (If Applicable) tPAF
(1)
tENH
PAF
Full - (m+1) words in FIFO
Full - m words in FIFO(2) tSKEW2 (3) tPAF
RCLK
REN1, REN2
tENS
tENH
2655 drw 12 NOTES: 1. PAF offset = m. 2. 8192 - m words in FIFO IDT72251. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge. 4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
5.14
13
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLKH WCLK
tCLKL
tENS
tENH
WEN1
tENS WEN2 (If Applicable) tENH
(1)
PAE
n words in FIFO tSKEW2 (2) tPAE
n+1 words in FIFO tPAE
(3)
RCLK
REN1, REN2
tENS tENH
2655 drw 13
NOTES: 1. PAE offset = n. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge. 3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW. Figure 11. Programmable Empty Flag Timing
5.14
14
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH WCLK tENS tENH tCLKL
LD
tENS
WEN1
tDS tDH
D0 - D7 PAE OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (LSB) PAF OFFSET (MSB)
2655 drw 14
Figure 12. Write Offset Registers Timing
tCLK tCLKH RCLK tENS tENH tCLKL
LD
tENS
REN1, REN2
tA Q0 - Q7 DATA IN OUTPUT REGISTER EMPTY OFFSET (LSB) EMPTY OFFSET (MSB) FULL OFFSET (LSB) FULL OFFSET (MSB)
2655 drw 15
Figure 13. Read Offset Registers Timing
5.14
15
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - A single IDT72251 may be used when the application requirements are for 8192 words or less. When the IDT72251 is in a Single Device
Configuration, the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
RESET ( WRITE CLOCK (WCLK) WRITE ENABLE 1 ( WRITE ENABLE 2/LOAD (WEN2/ ) ) IDT 72251
) READ CLOCK (RCLK) READ ENABLE 1 ( OUTPUT ENABLE ( DATA OUT (Q0 - Q8) EMPTY FLAG ( ) )
3545 drw 16
) )
DATA IN (D0 - D8) FULL FLAG ( PROGRAMMABLE ALMOST FULL ( ) )
PROGRAMMABLE ALMOST EMPTY ( READ ENABLE 2 ( )
Figure 14. Block Diagram of Single 8192 x 9 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (AE and AF) can be detected from any one device. Figure 15 demonstrates a 18-bit word width by
using two IDT72251. Any word width can be attained by adding additional IDT72251s. When the IDT72251is in a Width Expansion Configuration, the Read Enable 2 (REN2) control input can be grounded (see Figure 15). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
RESET ( DATA IN (D) 18 9
) 9
RESET (
)
READ CLOCK (RCLK) WRITE CLOCK (WCLK) WRITE ENABLE1 ( WRITE ENABLE2/LOAD (WEN2/ FULL FLAG ( FULL FLAG ( PROGRAMMABLE ( ) ) ) #1 ) #2 ) 9
IDT 72251 IDT 72251
READ ENABLE ( OUTPUT ENABLE ( PROGRAMMABLE (
) ) )
EMPTY FLAG ( ) #1 EMPTY FLAG ( ) #2 9 DATA OUT (Q)
18
READ ENABLE 2 (
)
READ ENABLE 2 (
)
3545 drw 17
Figure 15. Block Diagram of 8192 x 18 Synchronous FIFO Used in a Width Expansion Configuration
5.14
16
IDT72251 CMOS SyncFIFOTM 8192 x 9
COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION - The IDT72251 can be adapted to applications when the requirements are for greater than 8192 words. The existence of two enable pins on the read and write port allow depth expansion. The Write Enable 2/Load pin is used as a second write enable in a depth expansion configuration thus the Programmable flags are set to the default values. Depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. A typical application would have the expansion logic alternate data
access from one device to the next in a sequential manner. The IDT72251 operates in the Depth Expansion configuration when the following conditions are met: 1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a second Write Enable. 2. External logic is used to control the flow of data. Please see the Application Note" DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details of this configuration.
ORDERING INFORMATION
IDT
XXXXX Device Type
X Power
XX Speed
X Package
X Process/ Temperature Range
BLANK
Commercial (0C to +70C)
J
Plastic Leaded Chip Carrier (PLCC)
15 20 25 35
Com'l. Only
Clock Cycle Time (tCLK) Speed in ns
L
Low Power
72251
8192 x 9 Synchronous FIFO
3545a drw 18
5.14
17

▲Up To Search▲

Price & Availability of IDT72251L20J

	To Download IDT72251L20J Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .